Job Type
Job Details
- Master's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
- Experience in developing software systems in modern C++.
- Experience in computer architecture performance analysis and optimization.
- Experience in applying computer architecture principles to solve open-ended problems.
Preferred qualifications:
- Experience with Python.
- Experience in hardware/software co-design.
- Experience in analyzing workload performance and creating benchmarks.
- Knowledge of processor design and/or accelerator designs, mapping ML models to hardware architectures.
- Knowledge of design of digital logic at the Register Transfer Level (RTL) using Verilog.
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
In this role, you will work with Chip and Software architects to define the important blocks and flows that need to be modeled to provide insights into the behavior of the Accelerator. You will also work with the team to build the model, and use the model for architectural and micro architectural exploration to help define the Accelerator.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $124,000-$182,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
- Work with ASIC and Software architects to develop an architectural model for a hardware Accelerator.
- Contribute to the development of a shared infrastructure with reuse and scalability as the goal.
- Design experiments that enable the exploration of an architectural space for a given chip, collect and analyze the data, and inform the architectural choices made for a chip or system.
- Correlate observed results from Silicon with Architectural model and refine/calibrate model.
- Work closely with Software and Hardware teams on functionality, interfaces, and documentation.
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