Senior Field Programmable Gate Array (FPGA) Design Engineer - Requisition ID 108121

Salt Lake City, UT, United States Posted 8 days ago
Main Location
United States
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Employees at L3 Communication Systems-West create solutions that save lives. Join our team and serve those who serve us.

Who is L3 Communication Systems-West (L3 CSW)?

With over 3400 employees, we are one of Utah’s top employers. Our smart devices send mission-critical data into armed conflicts to help our troops stay safe by staying in touch with key information. We’ve taken large communications systems—ground based, mobile, satellite, surveillance and reconnaissance—and developed new ways to make them smaller and more capable.

Why should you work at L3 CSW?

Not only can you make life-saving differences for our troops, but at L3 CSW, you can have a flexible work schedule, buy up to 80 hours of additional vacation, access our on-site health clinic, work out in our on-site fitness center, eat in our on-site cafes with healthy food discounts, ride our shuttles or bicycles around our campus, take advantage of our tuition reimbursement, access L3 Perks, and so much more!

Who works at L3 CSW?

We are committed to diversity in every aspect of our business. Our inclusive culture welcomes all employees and values their unique contributions to our success. For L3 CSW, diversity enhances our business.

Are you ready to be L3 CSW?

Join us as we keep our nation and troops safe by providing life-saving solutions for use on sea, land, air, and space.

We are is seeking a Senior Field Programmable Gate Array (FPGA) Design Engineer with industry experience in the modem and/or digital signal processing (DSP) arenas.

Areas of desired expertise include:

  • Modulation
  • Demodulation
  • Forward Error Correction (FEC)
  • Digital filters
  • High-speed serial interfaces
  • Embedded Processors
  • Industry standard interfaces (e.g. Ethernet, SPI, UART, SDRAM, DDR, PCIe, JESD & VITA-49).
  • BSEE Required (MSEE preferred).
  • Must have 5+ years experience implementing complex modem and/or DSP circuits in programmable logic using FPGA devices.
  • Equivalent experience in ASIC design will also receive consideration.
  • Expertise in either VHDL (preferred) or Verilog development languages.
  • Expertise in simulation, synthesis, and placement software tools such as ModelSim, Synplicity, Xilinx and/or Altera development tool sets.
  • Expertise in laboratory debug techniques using digital scopes, logic analyzers, BERTS, and other complex measurement devices.
  • Familiarity with Linux, Git, and Clearcase code is a plus.
  • Familiarity with C/C++, Open CL and Matlab/Simulink is also a plus.
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