Position:
Design Verification Engineer
Job Description:

Responsibilities:
• Must be a quick learner, independent and communicate well.
• Knowledge and hands on experience with Verilog, System Verilog , UVM, debugging waveforms
• Building a testbench for a medium complexity block using System Verilog and UVM
• Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM.
• Developing, maintaining and supporting of the UVM verification environment.
• Debugging tests with design engineers to deliver functionally correct design blocks
• OOPS, randomization, constraints, interfaces
• Writing & analyzing functional coverage, assertions
• Generating and analyzing code coverage & writing waivers
Must have Skills::
• System Verilog, UVM expertise
• Excellent Python scripting skills
• PCIe or equivalent protocol experience
• 7 years' experience & above

EDUCATION BACKGROUND: Masters or bachelor's degree in engineering.

Annual Hiring Range/Hourly Rate:

Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.

Location:
US-CA-California (Remote Employees)

Remote work employees may be required to be present at the closest designated Arrow office for work-related purposes, at the Company's request and sole discretion.
Time Type:
Full time
Job Category:
Engineering Services

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)

Arrow COVID-19 Vaccination Policy:

Arrow requires all new employees in the United States to provide proof of full COVID-19 vaccination prior to beginning work, except where prohibited by law.