CMOS Technology and PPA Analysis Engineer, Platforms

Full Time
Main Location
Mountain View, CA, United States
Open jobs

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering or equivalent practical experience.
  • 6 years of work experience in IC development in FinFET process nodes.
  • Experience in working with foundry vendors and managing foundry design kit collaterals.
  • Experience in circuit design and simulations, signal and power analysis.

Preferred qualifications:

  • Experience with low power design techniques, power gating, multi-voltage designs, UPF/CPF and chip power management.
  • Experience in solving high performance chip design challenges across various technologies (embedded processors, DDR, networking fabrics, etc.).
  • Fundamentals in ASIC chip implementation (i.e., digital design, mixed mode digital and analog circuit design, physical design, integration, EDA tools, power optimization, block composition and timing, power and EM/IR analysis).
  • Understanding of advanced foundry process nodes and its interaction with assembly process and different package technologies.
  • Excellent communications skills with the ability to influence others with your technical visions and attention to detail.
About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a CMOS Technology and PPA Analysis Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a CMOS Technology and PPA Engineer, you will help to shape and influence advanced CMOS transistor and SRAM performance and co-develop with the IP ecosystem so our chip designs result in exceptional PPA to power our data centers. You will perform technical simulations and evaluations of foundry CMOS process nodes, custom or semi-custom circuit library and memory designs, mixed-signal and analog circuit peripherals and sensors and physical chip composition techniques and methodologies. You will collaborate with teams across Google to identify and create strategic opportunities for custom silicon innovation to deliver high systems impact.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
  • Perform technical evaluations on foundry CMOS process transistors, analog/mixed-signal IP vendor designs and/or custom SRAM memory implementations and provide recommendations.
  • Work with architecture and microarchitecture teams to evaluate custom circuit implementation for PPA optimizations.
At Google, we don’t just accept difference—we celebrate it, we support it, and we thrive on it for the benefit of our employees, our products and our community. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form.

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CMOS Technology and PPA Analysis Engineer, Platforms
Google LLC