Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. We are looking for talented individuals with deep experience that spans one or more of the key areas required to build successful world-class complex SoC and IP for data center applications. ASIC Engineer, Design Responsibilities:

• Architecture exploration
• Micro-architecture development
• RTL development using Verilog, System Verilog and HLS
• Soft and hard IP identification, selection and integration
• Collaboration with verification and emulation teams in test plan development and debug
• Collaboration with implementation team to close the design on timing and power

Minimum Qualifications:

• 15+ years of experience in micro-architecture and RTL development for complex control and data path IPs
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• Experience in leading complex SOCs or IP subsystems

Preferred Qualifications:

• Experience in data path development
• Experience in CPU, Network protocols, NOC, Memory and Peripheral Subsystems
• Experience with Synthesis, Timing Closure and Formal Verification Methodology
• Master’s or PhD degree in Electrical Engineering, Computer Science or related areas

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