Facebook is hiring ASIC Design Engineers within our Infrastructure organization. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center applications. ASIC Engineer, Design Responsibilities:

• Micro-architecture development
• RTL development using Verilog, System Verilog and HLS
• Lint, CDC, Synthesis, & Power Optimization
• Soft and hard IP identification, selection and integration
• Collaboration with verification and emulation teams in test plan development and debug
• Collaboration with implementation team to close the design on timing and power

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• At least 3+ years of silicon development experience
• Experience with Verilog or System Verilog
• Experience in one of these skills (minimum 3 years): Micro-architecture and RTL development for complex control and data path IPs, OR Experience in SoC Micro-architecture, Design and Integration, OR Implementation, Power methodology development

Preferred Qualifications:

• Experience in data path development
• Experience with Synthesis and Timing Closure

About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.