Physical Design Engineer, Methodology

Full Time
Main Location
Mountain View, CA, United States
Open jobs

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • Experience scripting in Python, Tcl, or Perl.
  • Experience with chip finishing issues for advanced process nodes.
  • Experience in ASIC physical design and physical design flows (i.e., synthesis, place and route, STA, formal verification, CDC) and methodologies in advanced nodes.

Preferred qualifications:

  • Master's degree in Electrical Engineering.
  • 5 years of experience in ASIC physical design and physical design flows (i.e., synthesis, place and route, STA, formal verification, CDC) and methodologies in advanced nodes.
  • Experience driving large physical design and CAD teams, delivering high performance SOCs.
  • Experience in hierarchical ASIC P&R and flow development. Multiple foundry experience.
  • Knowledge of semiconductor device physics and transistor characteristics. Knowledge of Verilog/System Verilog.
  • Experience extracting design parameters, QOR metrics, and analyzing trends and experience in IP integration (i.e., memories, IO’s, Analog IP).
About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a Physical Design Engineer on the chip implementation team, you will work on the physical implementation of ASICs using advanced technology nodes. You will develop physical design methodologies, automation scripts, and write documentation. You will perform technical evaluations of vendors, process nodes, and IP and will provide recommendations. Additionally, you will work with architecture, logic design, and DFT teams to understand and implement their requirements.

  • Develop, support and execute implementation flows, including synthesis, floorplanning, place and route, power/clock distribution, extraction, static timing analysis, CDC, formal verification, physical verification, and power integrity.
  • Perform technical evaluations of EDA tools and provide recommendations.
  • Work with EDA vendors to resolve tool issues and bugs.
  • Provide documentation, training, and support.
  • Solve block level issues including synthesis, macro placement, place and route, congestion analysis, timing closure, and formal verification.
At Google, we don’t just accept difference—we celebrate it, we support it, and we thrive on it for the benefit of our employees, our products and our community. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form.

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Physical Design Engineer, Methodology
Google LLC