Job Type
Full Time
Job Details
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience in developing and utilizing verification components and environments within the UVM framework.
- Experience in SystemVerilog for ASIC RTL verification.
- Experience in object-oriented programming.
Preferred qualifications:
- Experience in ASIC performance verification, including ASIC components.
- Experience in verification techniques, including System Verilog Assertions (SVA) and assertion-based verification.
- Experience with image processing or other multimedia IPs, such as display or video codec.
- Knowledge of ASIC standard interfaces and memory system architecture.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. - Collaborate with design engineers to fully comprehend design specifications and pinpoint critical verification scenarios for intricate multimedia digital design blocks.
- Develop and refine constrained-random verification environments utilizing System Verilog and Universal Verification Methodology (UVM).
- Define and implement comprehensive coverage metrics for stimulus and corner-cases.
- Work with design engineers to debug tests and ensure the functional of design blocks.
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