- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- Digital design experience using SystemVerilog RTL.
- 4 years of digital design experience.
- Experience interacting with software, architecture, and other cross-functional teams.
- Experience applying computer architecture principles to solve open-ended problems.
- Knowledge of processor design, accelerators, and/or memory hierarchies.
As a RTL Design Engineer, you will be part of a team developing cutting-edge ASICs used to accelerate computation in data centers. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $124,000-$182,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
- Create and review Compute subsystem's design microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with Design Validation (DV) teams to create testplans to verify and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.