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- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 5 years of experience in DFT specification definition architecture and insertion.
- 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent).
- Experience with ASIC DFT synthesis, STA, simulation, and verification flow.
- Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
Preferred qualifications:
- Master's degree in Electrical Engineering.
- Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).
- Experience in SoC cycles, including silicon bring-up and silicon debug activities.
- Experience in fault modeling.
In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.
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- Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. Demonstrate ownership from DFT logic, pre-silicon verification, to co-work with test engineers post silicon.
- Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks.
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
- Document DFT architecture and test sequences, including boot-up sequence associated with test pins.
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support post-silicon test team.
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