Senior Lead Engineer (FPGA)(Hybrid)
Onsite
Bangalore, India
Bangalore, India
Full Time Posted 13 days ago
Job Type
Full Time
Job Details
Date Posted:2024-01-28 Country:India Location:North Gate Business Park Sy.No 2/1, and Sy.No 2/2, KIAL Road, Venkatala Village, Chowdeshwari Layout, Yelahanka, Bangalore, Karnataka 560064 Position Role Type:Unspecified Job Title: Senior Lead Engineer Overview: In this role the ASIC/FPGA Verification Engineers Own and drive verification related activities, provide technical support, and proactively manage tasks to meet schedule goals. Also, actively participate in a team environment, working with verification, architecture, applications, and design teams to develop comprehensive verification plans and address issues. Primary Responsibilities:
- Develop an effective suite of tests and test environments using SystemVerilog UVM based tests to achieve predefined requirement verification goals.
- Experience in writing Agents, Drivers, Monitors, Predictors, Scoreboard, and Sequences etc.
- Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing.
- Experience in debugging VHDL based design.
- Experience in developing VHDL based verification environment.
- Actively participate in a team environment, working with verification, architecture, applications, and design teams to develop comprehensive verification plans and address issues.
- Verification environment development/update for block level and system level.
- Own and drive verification related activities, provide technical support, and proactively manage tasks to meet schedule goals.
- Help define and develop effective functional assertions and cover points
- Verify structural and functional coverage of module and system level test suite.
- Advanced skills in various programming languages such as Verilog, System Verilog, PERL
- Apply techniques and skills required to identify a root cause of a given issue and very good debugging skills.
- Technical guidance to the junior engineers on verification tasks.
- Must be ready for travel to abroad on need basis
- 9+ years of Industry experience with experience in development, integration & verification of ASIC/FPGA.
- Bachelor's/Master's degree in Engineering (ECE,VLSI)
- Minimum one project executed as a Project Lead role for avionics FPGA verification.
- Minimum 3 years experience in debugging VHDL RTL design.
- Minimum 6 years of experience in developing System Verilog UVM verification environment components such as Agents, Drivers, Monitors, Predictors, Scoreboard, and Sequences.
- Minimum 5 years of experience with Questasim or similar advanced simulation tools.
- Minimum one project experience in DO-254 verification process.
- Minimum 5 years of experience in developing functional coverage, assertions and constrained random stimulus with SV/UVM.
- One year of experience in DOORS/Jama will be a plus.
- One year of experience in the video domain will be a plus.
- Background check required (every external new hire in the India)
- Drug Screen only performed for Operations Positions
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