Minimum qualifications:

• Bachelor's degree in electrical/computer engineering, computer science, a related field, or equivalent practical experience.
• 3 years of experience in Verilog or SystemVerilog.
• 1 year of experience bringing up hardware functionality through Simulations/FPGAs/Emulation.
• Experience working on ASIC/FPGA design or verification.

Preferred qualifications:

• Master's degree or PhD in electrical/computer engineering, computer science, or a related field.
• 3 years of experience working on FPGA platforms or Emulation platforms with IPs (e.g., PCIe, DDR memory, Gigabit Ethernet, Flash).
• Experience developing architectures for Machine Learning Accelerators.
• Experience writing/debugging verilog/RTL code for ASIC/FPGA designs and waveform debug skills.
• Experience developing HW prototypes/SW models for early software development and develop end-to-end System validation strategies for an ASIC/FPGA product.
• Solid fundamentals in two of the following areas: computer architecture, FPGA system design, Interface IPs (DDR/PCIe/GbE).

About the job Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. The Platform Enablement team is responsible for the development, bringup and qualification, deployment, and sustaining quality of our custom silicon. We plan and integrate complex hardware and software stacks and operate them on emulation, simulation and FPGA platforms for pre-Silicon validation. In this role, you will help create software-based custom test cases, workloads, test generators, infrastructure, analysis tools, and debugging tools. In later phases, you will be responsible for silicon bringup, validation, characterization and qualification, and sustaining programs and their quality. You will help ensure our fleet runs at maximum efficiency, help debug problems, and root cause those issues. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities

• Enable bringup of Chip features through Firmware and driver stack. Integrate and validate complex hardware/software (HW/SW) designs in pre-silicon.
• Architect and Design ASIC models for Emulation/FPGA Prototypes. Design SoC configurations and IP models to optimize for simulation performance/run times.
• Create HW/SW co-simulation methodologies leveraging RTL simulation, Emulation, FPGA environments as appropriate. Design solutions to improve HW Modeling accuracy and Scale to various system configurations to improve Coverage.
• Bringup chip features/subsystems and drive debug discussions with cross-functional teams and help root-cause functional failures and performance issues. Review Architecture Specs, develop the integration plan with software and System partners, coordinate HW/SW delivery and Benchmark Performance.
• Plan and Design Validation tests and microbenchmarks to validate IP/SoC functionality, performance and collaborate with a cross-functional team (e.g., design, DV, firmware, compiler, Architecture).

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.