TPU ASIC Design Verification Engineer, Machine Learning
Onsite
United StatesSunnyvale, CA, United States
United States
Full Time Posted 15 days ago
Job Type
Full Time
Job Details
Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
- 3 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- Experience with SystemVerilog (i.e. SystemVerilog Assertions or functional coverage).
- Master's degree or PhD in Electrical Engineering.
- 6 years of work experience with full verification life cycle.
- Experience verifying digital logic at RTL using SystemVerilog for ASICs.
- Experience in Power aware verification, Gate level simulations, and Post silicon bring-up.
- Strong problem solver, communicator and team player.
- Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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