SOC Design Engineer
Onsite
United StatesSunnyvale, CA, United States
United States
Full Time Posted 10 days ago
Job Type
Full Time
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 2 years of experience in ASIC design flows and methodologies, with 1 year of experience in IP integration (e.g., subsystems, memories, IO's and Analog IP) and RTL design.
- Experience in scripting languages (e.g., Python, Tcl, or Perl) and with Verilog/System Verilog.
- Experience working on various technologies (e.g., embedded processors, DDR, SerDes, networking-on-chip fabrics, etc.).
- Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
- Experience with silicon, emulation, FPGA validation and debug, functional verification, physical design, and DFT methodologies.
- Experience with SOC implementation standards and interfaces.
- Experience with low power design techniques, power gating, multi-voltage designs.
- Experience with industry standard integration tools.
- Experience on recent technology nodes.
- Own the planning, creation, and delivery of top-level RTL/deliverables for ASIC and SOC projects from concept to working silicon volume.
- Resolve structural or functional issues related to the integration of ASICs and SOCs and collaborate with teams across Google to develop ideas for Silicon and hardware projects.
- Manage cross-functional interactions related to top-level RTL of chip projects.
- Improve cross-functional implementation methodologies to create consistency and efficiency across multiple parallel implementation teams and projects.
- Perform technical evaluations of vendors and IP, providing recommendations and assessment of process node tradeoffs to meet performance, power, area/cost goals.
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