Job Type
Job Details
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 2 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques.
- Experience with a scripting language such as Perl or Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience implementing image/video processing blocks or other multimedia IPs such as Display or ISP
- Experience with Application-Specific Integrated Circuit (ASIC) design methodologies for clock domain checks and reset checks
- Experience in scripting languages, C/C++ programming and software design skills.
In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes Micro architecture, RTL coding, definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews and closure for quality and optimized security designs. You will be involved in Micro-Arch and RTL coding for imaging and video codecs - IPs and subsystems. You will also contribute to improvements by debugging and by using different RTL QC tools like Lint, CDC, VCLP.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
- Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Perform RTL verification using industry standard methodologies. Participate in test planning and coverage analysis.
- Develop RTL implementations that meet competitive power, performance and area targets.
- Participate in synthesis, timing/power closure and Field-Programmable Gate Array (FPGA) or silicon bring-up.
- Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture or micro-architecture planning.
