Own the full verification life cycle: from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy targets. Build robust, constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of AI/ML workloads on TPU hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Develop and execute verification plans. Architect, develop, and maintain verification test benches that support both random and directed testing.
  
• Participate in design, architecture, and code reviews. Work closely with micro architects, architects and design teams, and influence design decisions/feature intercepts.
  
• Lead performance validation for both pre-silicon and post-silicon. Work with emulation/FPGA prototyping teams in verifying system level use cases.
  
• Drive convergence of verification and coverage plans towards high quality and on-time tape-out. Drive methodology initiatives to improve efficiency and design quality.
  
• Lead a team of design verification engineers focusing on IP, Subsystem/SoC verification at unit, cluster, subsystem, and full chip levels.