Onsite
Full Time Posted 16 days ago
I'm Interested

Job Type

Full Time

Job Details

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
  • 5 years of experience with verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog.
  • Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog and UVM for Application-Specific Integrated Circuits (ASIC).

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience creating and using verification components and environments in a standard verification methodology such as UVM.
  • Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification using Industry leading formal tools.
  • Experience with Google Line System (GLS), low-power DV, and support of SOC DV.
  • Experience with performance verification of ASICs and ASIC components, ASIC standard interfaces and memory system architecture, Low Power Double Data Rate (LPDDR).
About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities
  • Work with design verification and other stakeholders to come up with detailed test plans, dependencies, and deliverables.
  • Plan the verification of complex Memory Subsystem IPs at Internet Protocol (IP) and Subsystem level by understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
  • Work closely with design, architecture, software, silicon validation, and back-end implementation stakeholders to make technical decisions.
  • Create and enhance constrained random verification environments using System Verilog and Universal Verification Methodology (UVM), or formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
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Senior Design Verification Engineer
I'm Interested