In this role, you will perform formal verification of design properties of complex ASIC designs. You will collaborate closely with Design and Verification Engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. You will help define and improve design and verification methodologies that allow you to achieve formal verification closure. This is a central role that will require you to interact with multiple Design teams.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

• Plan the formal verification strategy, create the properties and constraints for complex digital design blocks.
  
• Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
  
• Resolve difficult to verify properties.
  
• Contribute improvements to methodologies to enhance formal verification results.
  
• Architect and implement reusable formal verification components.