Job Type
Full Time
Job Details
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of industry experience in the SI/PI field.
- Experience in chip package SI/PI design for interconnections and advanced package design.
Preferred qualifications:
- Experience in post silicon correlation with models.
- Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking.
- Experience in cross-functional collaboration with chip top design, physical design, STA, package, system design, and validation teams.
- Experience in programming and data analysis with Matlab, Python, C++ and statistical tools to establish automation flows and data processing.
- Understanding of on and off chip power delivery and STA/voltage budget.
- Familiarity with memory testing, next generation memory, chiplet standards and timing budget methodology.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package and system level.
You will be the part of a larger team with Chip Architects, ASIC Engineers, Physical Design and other SI/PI Engineers. You will work with various cross-functional teams, including Chip Design, System Design, software team and vendors. You will drive chip packaging signal and power implementations from product planning to New Product Introduction (NPI).
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. - Contribute to chip-package-system co-design by performing Signal Integrity (SI)/Power Integrity (PI) analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for High Performance Computing (HPC) based on 2.5D/3D package technology.
- Develop next generation IO interfaces (serdes, memory, D2D) considering IO PHY, SI/PI and physical design.
- Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design target, unleash boundaries of chip performance and explore SI/PI and DFM tradeoff for advanced package design closure for production.
- Provide feedback on chip floorplan considering IP performance/package/system routability and SI/PI.
- Conduct post silicon validation and qualification of high speed interface for NPI.
Company Details
Google Inc.
Mountain View, CA, United States
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