Job Type
Full Time
Job Details
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel. Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- Experience working with design networking like: Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
- Experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
- Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
- Experience in leading chip development projects.
Preferred qualifications:
- Master's or PhD degree in Engineering or equivalent practical experience.
- Proficiency with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
- Knowledge of data center and cloud markets, technological and business trends, requirements, and ecosystem partners.
- Ability to motivate and focus a large collaboration to reach testing goals.
- Excellent communication and facilitation skills.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be responsible for overseeing the design and development of cutting-edge chip for our innovative products.You will be responsible for leading the chip design end to end, from architecture requirements up to tape-out.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. - Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, Planning and tracking.
- Coordinate the work of different disciplines, such as design, verification, and test, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager (TPM), Design verification lead, Professional Development (PD) lead, Design for Testing lead, Design lead and architecture team, to make execution decisions and drive the development process.
- Resolve complex technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures.
- Lead the project development with excellent quality and address issues throughout the design and implementation phases.
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