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Job Type
Full Time
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with hardware description languages (RTL) such as verilog and systemverilog.
- Experience in creating and using verification components and environments in standard verification methodology.
- Experience in RTL development for ASIC subsystems using System Verilog/UVM, and overall chip design flow.
- Experience with design management of SoCs in process nodes.
- Experience with Verification Techniques.
- Plan tasks, hold code and design reviews, contribute on sub-system/chip-level integration, and perform all the required verification tasks.
- Interact with the architecture team and develop implementation strategies to meet quality, schedule, and power performance areas for sub-system/chip-level integration.
- Plan SOC milestones and quality checks, and guide subsystem teams with SOC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.).
- Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
About the Company
Google Inc.
Mountain View, CA, United States
Build for everyone Since our founding in 1998, Google has grown by leaps and bounds. Starting from two computer science students in a university... Read more