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Job Type
Full Time
Job Details
Google welcomes people with disabilities. Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with low-power dynamic and leakage, power estimation, as well as data analytics, and profiling.
- Experience in flow automation (e.g., Python, C, C++).
- 3 years of experience in RTL design and low-power design techniques.
- Experience with the concept of power management, retention, or Dynamic Voltage and Frequency Scaling (DVFS).
- Experience with vendor tools (e.g., PTPX, Ansys Power Artist, Synopses Prime Power RTL).
- Experience with CPU bench-marking, performance analysis, and competitive study.
- Knowledge of CPU micro-architecture.
- Own and drive several activities related to architecture energy modeling, engaged performance and power analysis, power optimization, simulation and rollups.
- Collaborate with the SoC Power Team in Taiwan on various power projections and requirements for our CPU, including silicon power capture of participant CPUs for benchmarks and other daily workloads.
- Perform data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation.
About the Company
Google Inc.
Mountain View, CA, United States
Build for everyone Since our founding in 1998, Google has grown by leaps and bounds. Starting from two computer science students in a university... Read more