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Job Type
Full Time
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with digital design in ASIC.
- 4 years of experience in people management.
- Experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience with ARM-based SoCs, interconnects, and ASIC methodology.
- Master’s degree in Electrical Engineering or Computer Engineering.
- Experience with methodologies for low power estimation, timing closure, and synthesis.
- Experience leading IP/SoC design team for low power SoCs.
- Ability to drive a multi-generational roadmap for IP/SoC development.
- Lead a team that delivers fabric interconnect IP, platforms, and subsystems.
- Drive multi-generation roadmap for design optimization.
- Define micro-architecture details (e.g., interface protocol, block diagram, data flow, pipelines, etc.).
- Oversee RTL development, debug functional, and performance simulations.
- Participate in synthesis, timing/power estimation, and Field-Programmable Gate Array/silicon bring-up.
About the Company
Google Inc.
Mountain View, CA, United States
Build for everyone Since our founding in 1998, Google has grown by leaps and bounds. Starting from two computer science students in a university... Read more